On-chip networks /
This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. It is a resource for both understanding on-chip...
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Main Authors: | , , |
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Format: | Electronic eBook |
Language: | English |
Published: |
Cham, Switzerland :
Springer,
[2017]
|
Edition: | Second edition. |
Series: | Synthesis lectures in computer architecture ;
#40. |
Subjects: | |
Online Access: | Connect to this title online |
Table of Contents:
- 1. Introduction
- 1.1 The advent of the multi-core era
- 1.1.1 Communication demands of multi-core architectures
- 1.2 On-chip vs. off-chip networks
- 1.3 Network basics: a quick primer
- 1.3.1 Evolution to on-chip networks
- 1.3.2 On-chip network building blocks
- 1.3.3 Performance and cost
- 1.4 This book, second edition.
- 2. Interface with system architecture
- 2.1 Shared memory networks in chip multiprocessors
- 2.1.1 Impact of coherence protocol on network performance
- 2.1.2 Coherence protocol requirements for the on-chip network
- 2.1.3 Protocol-level network deadlock
- 2.1.4 Impact of cache hierarchy implementation on network performance
- 2.1.5 Home node and memory controller design issues
- 2.1.6 Miss and transaction status holding registers
- 2.1.7 Brief state-of-the-art survey
- 2.2 Message passing
- 2.2.1 Brief state-of-the-art survey
- 2.3 NoC interface standards
- 2.4 Conclusion.
- 3. Topology
- 3.1 Metrics
- 3.1.1 Traffic-independent metrics
- 3.1.2 Traffic-dependent metrics
- 3.2 Direct topologies: rings, meshes, and Tori
- 3.3 Indirect topologies: crossbars, butterflies, Clos networks, and fat trees
- 3.4 Irregular topologies
- 3.4.1 Splitting and merging
- 3.4.2 Topology synthesis algorithm example
- 3.5 Hierarchical topologies
- 3.6 Implementation
- 3.6.1 Place-and-route
- 3.6.2 Implication of abstract metrics
- 3.7 Brief state-of-the-art survey.
- 4. Routing
- 4.1 Types of routing algorithms
- 4.2 Deadlock avoidance
- 4.3 Deterministic dimension-ordered routing
- 4.4 Oblivious routing
- 4.5 Adaptive routing
- 4.6 Multicast routing
- 4.7 Routing on irregular topologies
- 4.8 Implementation
- 4.8.1 Source routing
- 4.8.2 Node table-based routing
- 4.8.3 Combinational circuits
- 4.8.4 Adaptive routing
- 4.9 Brief state-of-the-art survey.
- 5. Flow control
- 5.1 Messages, packets, flits, and phits
- 5.2 Message-based flow control
- 5.2.1 Circuit switching
- 5.3 Packet-based flow control
- 5.3.1 Store and forward
- 5.3.2 Virtual cut-through
- 5.4 Flit-based flow control
- 5.4.1 Wormhole
- 5.5 Virtual channels
- 5.6 Deadlock-free flow control
- 5.6.1 Dateline and VC partitioning
- 5.6.2 Escape VCs
- 5.6.3 Bubble flow control
- 5.7 Buffer backpressure
- 5.8 Implementation
- 5.8.1 Buffer sizing for turnaround time
- 5.8.2 Reverse signaling wires
- 5.9 Flow control in application specific on-chip networks
- 5.10 Brief state-of-the-art survey.
- 6. Router microarchitecture
- 6.1 Virtual channel router microarchitecture
- 6.2 Buffers and virtual channels
- 6.2.1 Buffer organization
- 6.2.2 Input VC state
- 6.3 Switch design
- 6.3.1 Crossbar designs
- 6.3.2 Crossbar speedup
- 6.3.3 Crossbar slicing
- 6.4 Allocators and arbiters
- 6.4.1 Round-robin arbiter
- 6.4.2 Matrix arbiter
- 6.4.3 Separable allocator
- 6.4.4 Wavefront allocator
- 6.4.5 Allocator organization
- 6.5 Pipeline
- 6.5.1 Pipeline implementation
- 6.5.2 Pipeline optimizations
- 6.6 Low-power microarchitecture
- 6.6.1 Dynamic power
- 6.6.2 Leakage power
- 6.7 Physical implementation
- 6.7.1 Router floorplanning
- 6.7.2 Buffer implementation
- 6.8 Brief state-of-the-art survey.
- 7. Modeling and evaluation
- 7.1 Evaluation metrics
- 7.1.1 Analytical model
- 7.1.2 Ideal interconnect fabric
- 7.1.3 Network delay-throughput-energy curve
- 7.2 On-chip network modeling infrastructure
- 7.2.1 RTL and software models
- 7.2.2 Power and area models
- 7.3 Traffic
- 7.3.1 Message classes, virtual networks, message sizes, and ordering
- 7.3.2 Application traffic
- 7.3.3 Synthetic traffic
- 7.4 Debug methodology
- 7.5 NoC generators
- 7.6 Brief state-of-the-art survey.
- 8. Case studies
- 8.1 MIT Eyeriss (2016)
- 8.2 Princeton Piton (2015)
- 8.3 Intel Xeon-Phi (2015)
- 8.4 D E Shaw Research Anton 2 (2014)
- 8.5 MIT SCORPIO (2014)
- 8.6 Oracle Sparc T5 (2013)
- 8.7 University of Michigan Swizzle Switch (2012)
- 8.8 MIT Broadcast NoC (2012)
- 8.9 Georgia Tech 3D-MAPS (2012)
- 8.10 KAIST Multicast NoC (2010)
- 8.11 Intel Single-chip Cloud (2009)
- 8.12 UC Davis AsAP (2009)
- 8.13 Tilera TILEPRO64 (2008)
- 8.14 ST Microelectronics STNoC (2008)
- 8.15 Intel TeraFLOPS (2007)
- 8.16 IBM Cell (2005)
- 8.17 Conclusion.
- 9. Conclusions
- 9.1 Beyond conventional interconnects
- 9.2 Resilient on-chip networks
- 9.3 NoCs as interconnects within FPGAs
- 9.4 NoCs in accelerator-rich heterogeneous SoCs
- 9.5 On-chip networks conferences
- 9.6 Bibliographic notes
- References
- Authors' biographies.